The present invention relates generally to a method of forming semiconductor devices, and more particularly to a simplified method to integrate thin body silicon-on-insulator devices with “bulk” substrate devices.
A key electronic component in the integrated circuit (IC) is the planar, bulk metal-oxide semiconductor field effect transistor (MOSFET). A key driver for the IC industry has been the continuous reduction of the physical dimensions of the MOSFET. In the near future, traditional CMOS technology is expected to reach the limits of scaling. As the MOSFET gate dielectric is scaled down to a thickness of 1.5 nm, the gate leakage current increases sharply. Therefore, non-classical transistor structures will likely be implemented due to their higher performance with lower leakage than the limited conventional scaled CMOS approaches. Unique MOSFET structures such as ultra-thin body (UTB) MOSFETs and double gate MOSFETs offer paths to further scaling in the future. The UTB and double gate MOSFETs can be integrated with silicon-on-insulator ICs. These UTB silicon-on-insulator MOSFETs reduce short channel effects (SCE), increase IC performance and speed, and reduce power consumption. Also, additional design enhancements such as SOI ICs using strained silicon MOSFET technology, as well as dual silicon crystal orientation substrates have started to be implemented to further increase the IC performance.
“Silicon-on-insulator” (SOI) technology utilizes two separate silicon substrates in an IC. The SOI structure is typically comprised of three substrates: a single-crystal silicon layer SOI substrate with a thickness of 1 mm or less; a bulk silicon substrate; and a thin SOI to bulk insulator that electrically isolates the single-crystal layer substrate and the bulk substrate. This thin insulator layer inhibits the parasitic or incidental capacity normally produced between a device and the substrate in conventional wafers. The result is lower power consumption and higher processing speeds.
One method to improve IC performance is to implement UTB MOSFETs on a SOI wafer. In an UTB transistor, leakage current is controlled through the use of the body region, which is significantly thinner than the gate length, where gate lengths may be down to 20 nm in prevalent designs. The potential barrier for any path between the source and drain is more strongly coupled to the gate than the drain. This is accomplished by fabricating the body using a thin silicon film with a thickness approximately one half of the source to drain spacing. When a transistor is constructed with this thin body, the gate potential controls all source-to-drain current paths. As the gate modulates the potential of the channel region, it also modulates the potential of all the other sub-surface leakage paths, thus the UTB transistor does not rely on body doping to provide a potential barrier between its source and its drain. In UTB SOI structures, control of SCE and the adjustments of the threshold voltage (Vt) can be realized with little or no channel doping.
Another method to improve IC performance is to implement double gate MOSFETs on a SOI wafer. Double gate MOSFETs are similar to single gate transistors, except that a second (bottom) gate electrode, which is fully self-aligned to the first (top) gate electrode, is added. The double gate MOSFET has superior control of SCE due to the electrical shielding effects of the bottom gate. It has near ideal sub-threshold slope and mobility enhancement. A double gate MOSFET controls roughly twice as much current as a single gate MOSFET. In addition, the double gate design provides inherent electrostatic and hot carrier coupling in the channel. However, double gate MOSFETs are not commonly implemented because its fabrication is more complex and requires a higher fabrication cost compared to the fabrication of single gate MOSFETs.
Yet another method to improve IC performance is to implement strained silicon MOSFET technologies, which provide high electron mobility by stretching the top silicon layer with an underlying layer of silicon germanium (SiGe). Strained silicon MOSFET incorporation has been proven to provide a 20 to 30 percent performance enhancement. Strained silicon MOSFET technologies can also be implemented on a SOI structure.
Yet another method to improve IC performance is to implement a dual silicon crystal orientation substrate, which is also called a hybrid-orientation substrate. For example, one known implementation, called “Hybrid Orientation Technology”, gives a 40 to 65 percent performance enhancement by increasing the mobility of the positive charges, or holes, through the device channels. In that implementation, CMOS ICs consist of positively charged field effect transistors (PFETs) and negatively charged field effect transistors (NFETs). For PFETs, hole mobility is known to be 2.5 times higher on a silicon crystal orientation (110) surface compared to that on a standard silicon crystal orientation (100) surface. Therefore, by incorporating two substrates—a silicon (110) substrate and a silicon (100) substrate—a substantial performance enhancement can be achieved due to higher mobility on the silicon (110) substrate.
Some conventional designs integrate a SOI substrate with a Bulk substrate within an IC, which may also incorporate other implementations such as UTB MOSFETs, double gate MOSFETs, strained silicon MOSFETs, and a hybrid-orientation substrate. By utilizing these implementations, IC performance can be enhanced with allowances for future scaling. Although conventional designs permit the fabrication of an IC with the above structures, they are complex and very costly to implement.
Therefore, desirable in the art of SOI/Bulk structure semiconductor fabrication are improved structures that simplify the fabrication processes, thereby reducing fabrication costs and maintaining allowances for future scaling.